Mironova Labs · Technical Resource

Application-Specific Process Notes

Integration guidance for high-k dielectrics, Cu interconnects, III-V passivation, and optical coatings

ApplicationsZr / Cu / Gd Systems

High-k Gate & DRAM Capacitor Dielectrics (ZrO₂)

As DRAM scales sub-10 nm, capacitor dielectrics require ultra-low EOT combined with negligible leakage to maintain data retention. ALD ZrO₂ in MIM stacks (TiN/ZrO₂/TiN or Ru/ZrO₂/TiN) is the industry standard.

Optimize Zr(TMHD)₄ with high-concentration O₃ at 390–400 °C to promote in-situ crystallization of the tetragonal ZrO₂ phase (k ≈ 30–40 vs ~20 for monoclinic).
Total absence of residual halides prevents localized chemical corrosion of sensitive TiN bottom electrodes (a known failure mode with ZrCl₄).
Target physical thickness: 5–8 nm. Below this, unacceptable leakage from direct quantum mechanical tunneling. Above this, capacitance density is insufficient for advanced nodes.
Published dielectric performance for Zr(TMHD)₄-derived ZrO₂: k = 24–32, leakage 3.3 × 10⁻⁶ A/cm² at 1 MV/cm.

Cu Interconnects & Conformal Seed Layers

As interconnect pitch scales below 30 nm, PVD copper sputtering fails to provide continuous, conformal seed layers inside high-aspect-ratio vias. Discontinuous seeds cause fatal void formation during electrochemical plating.

Integration stack: conformal ALD TaN diffusion barrier → ultra-thin ALD or PVD Ru liner → Cu(TMHD)₂ ALD seed (sub-5 nm).
Cu(TMHD)₂ reduced by H-plasma nucleates seamlessly on Ru surfaces, yielding pinhole-free continuous seed layers capable of carrying plating current.
Direct Cu ALD on bare TaN or SiO₂ without the Ru liner will result in agglomerated, highly resistive nanoparticles and guaranteed via failure.
Best reported Cu(TMHD)₂ film resistivity: ~8 µΩ·cm at 60 nm (approaching bulk Cu at 1.72 µΩ·cm). At 25 nm: ~15 µΩ·cm due to grain boundary/surface scattering.

III-V Channel Passivation (Gd₂O₃)

High-mobility InGaAs channels in advanced logic devices are plagued by interface trap states (Dᵢₜ) that pin the Fermi level, degrade carrier mobility, and destroy drive current. Gd₂O₃ from Gd(TMHD)₃ provides exceptional passivation.

The Gd(TMHD)₃/O₃ process chemically assists in the thermodynamic displacement and reduction of problematic native arsenic and gallium oxides on the semiconductor surface.
Optimized Gd₂O₃/InGaAs interfaces yield Dᵢₜ as low as ~10¹² eV⁻¹ cm⁻² with negligible frequency dispersion in C-V measurements.
Published MOS data retains native SiO₂ at the interface — electrical values reflect Al/Gd₂O₃/native SiO₂/Si stacks, not pristine Gd₂O₃/Si interfaces. Interface-resolved characterization is needed for direct-on-Si targets.
Leakage current for ~50 nm Gd₂O₃ at 300 °C: <2×10⁻⁸ A/cm² at 1 V (significantly better than Cp/H₂O-derived films at <5×10⁻⁷ A/cm²).

Optical Coatings & Photonics

Gd₂O₃ is used as a high-refractive-index, wide-bandgap material for laser optics, precision sensors, and photonic devices.

The Gd(TMHD)₃/O₃ process is uniquely suited for optical applications: extremely low residual carbon ensures maximum transparency and minimum absorption across visible and near-IR spectra.
The slow GPC (0.3 Å/cycle) is an asset here: it enables sub-nanometer precision in multilayer Distributed Bragg Reflectors (DBRs) and anti-reflective nanolaminates where absolute thickness control is prioritized over throughput.
Surface roughness of ~1.2 nm rms at 250 °C (95 nm film) makes Gd(TMHD)₃-derived films suitable for optical interface quality requirements.

References

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[R2] Niinistö J, et al.. Atomic Layer Deposition of ZrO₂ Thin Films Using Zr(thd)₄ and Ozone, Thin Solid Films (2005). doi:10.1016/j.tsf.2005.08.360
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[R17] Kostić I, et al.. Gadolinium Scandate: Candidate for Alternative Gate Dielectric in CMOS Technology, J. Electrical Engineering (2011)